Hardware specialization and domain specific accelerators have recently enjoyed renewed interest as a way to bridge the performance gap and reduce the energy cost of computation. Unfortunately, the current methodologies and approaches to hardware design require significant engineering effort and domain expertise making the design process unscalable. In particular, codesign of application domains with the underlying hardware architecture is a daunting architectural design space which takes additional manual effort. This project seeks to introduce programming language techniques such as program synthesis to the hardware design process to generate custom reconfigurable accelerators to reduce the engineering burden required to design them.
